Functional Verification

Validate the correct functionality of your HDL Design or System without overhead

Our customers save development time by outsourcing requirements management and functional verification tasks to us. In cooperation with the developers, we build and deliver reasonably sized, self-checking testbenches.

  • VHDL (1993-2008), Verilog, SystemVerilog
  • OS-VVM (Workd with all FPGA development environments
  • Functional Verification of large distributed, connected systems (using our own Python libraries)
  • Development of Bus functional Models
  • Equivalency checks
  • Training and Documentation
  • Requirements management
  • Reengineering and correction of existing designs